I don't know much about chip fabrication but reading wikipedia I see this:
> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. ... a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers... "3 nm" is used primarily as a marketing term by individual microchip manufacturers ... there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node
So can someone who is more familiar with it help me understand what progress we're making in terms of the physical aspect of the chips? Is transistor density still increasing? Are we using different materials? At a physical level what's different about this generation of chips?
For the first version of TSMC 3nm, die sizes are projected to be ~42% smaller than TSMC 5nm and you have a choice of using ~30% less power or improving performance by ~15%.
While it's unlikely scaling continues to this level, I got this funny idea: eventually the marketing gate size might become smaller than a single atom!
We're close enough to see that on the horizon; about 2 angstroms is the width of a silicon atom. Or well, distance between two nuclei in a silicon lattice. 'Width' of an atom is a tricky concept with many definitions.
Hence AMD using different process nodes for the stuff that scales and the stuff that doesn't at the same time with their chiplets, so they can get the best of both worlds.
Didn't AMD start down the chiplet path way before the horrible SRAM scaling became clear? I was the under the impression they were chasing better yield and this is just another handy gain.
3D V-Cache in the only SKUs on the market right now (5800X3D and Milan-X) is 7nm, just like the CCD beneath it. IOD is Glofo 12nm on that.
On GPUs this strategy isn't working out too well for them right now. Their 7900 is a lot more silicon with a lot more transistors (300 mm² of N5, 220 mm² of N6, 58bn xtors) compared to the competition (380 mm² of N4, 46bn) [1] and is marginally faster in some cases, drastically slower in others, and uses much more power in every case.
[1] While AMD uses two slightly older processes, AIUI the overall packaging and silicon costs are speculated to be quite a bit higher for AMD compared to nVidia here.
I don't think comparing chiplet sizes by summing the area is a good way of doing it, because smaller nodes cost more and have lower yield, and smaller individual chiplets mean way less loss per-wafer, as the bigger the size of a single usable unit, the more chance something is broken and it isn't usable. Losing one or two small chiplets is a lot cheaper than losing entire chips in a monolithic setup.
AMD claim that producing a 16-core Ryzen CPU without chiplets would have cost them twice as much. You say that the GPU strategy isn't working out, but I think that really depends on what their pricing strategy is. I suspect they just don't feel they can take the market right now, and are making a lot of margin while the market will support it, rather than trying to compete on price at this moment, but I admittedly don't have any evidence for that.
I guess we'll see, but it sure seems like there is a lot of advantage to building the way they have to me, I'd personally be surprised if it didn't pay off.
Yes, transistor densities are increasing, interconnects are getting denser as well (that's what the "metal pitch" is about). There are also improvements in power consumption.
I imagine there is more use of EUV and surely material compositions are getting tweaks as well.
This is pretty much as it has been for the last couple of decades, though at a somewhat slower rate and with an increasing number of caveats. For example, the density of SRAM has recently been decreasing more slowly than the density of logic. What's particularly tricky are the economics: the cost per transistor isn't really going down much anymore.
Transistors at that scale are 3D rather than 2D, so the expected scaling ratios no longer apply. If you wanted double the density of a 2D transistor with 5nm features, you'd need to scale down to 3.5nm, but if you wanted to double the volumetric density in 3D, you'd only need to go down to 4nm.
How do you make meaningful compare to past generations with that being the case? You could then just describe it in 2D terms, and refer to your 4nm process as 3nm. Then all of the same rules of thumb still hold.
I assume this is responsible for at least some portion of the deviation and confusion, though maybe not all of it. Happy to be corrected if I'm wrong.
The industry roadmap has adopted a new nomenclature to try to clear this up, but it remains to be seen if the major companies will adopt it.
In any case, people who jump to saying these process node names are bullshit because they don't simply map to something like a wire width are kinda naively missing the point. Everyone in the industry understands what's going on and these fab node names emerged naturally as a shorthand way of describing changes to design rules that are a lot more complex and varied. That's still true today.
Also, in practice, no one cares how "tall" the chip is — 100nm vs 200nm is ... unimportant. The result is that the volume of the poly hasn't changed much in the last ~10 years. Transistors are still biggish; just with tiny footprints. (And really, it's pitch density: we can pack the poly tighter.)
Not quite. We basically don't care about 3D density at the moment. The plane of the wafer is ultimately what matters from a density perspective. Right now we're actively cutting into 3D density heavily for small 2D density gains.
I assume you care about 2D vs 3D for different variables, no? I agree 3D, at least while H<<W, doesn't matter for clock speeds, but wouldn't it still play a significant role in the power characteristics, particularly things like gate capacitance? Genuinely curious. Going off of my memory of my Physics of CompE class ~10 years ago at this point.
If the gates of the transistor are taking up all that space, but FinFETs and newer gate all around FETs have significantly sized voids in 3D space, you just can't practically use those voids for anything else without cutting into yields or having awful leakage issues.
Smaller marketing numbers generally do relate to improved performance, usually from minor optimizations across the board like needing to move less charge to switch a transistor, etc. Also certain numbers introduce things like FinFET or gate-all-around that further increase performance.
We are now past the point where just simple size shrink will yield significant benefit, due to physical limits no less. Most of the heavy lifting in terms of performance improvement comes from microarchitecture advancements
Look at FinFET transistors; this is the style of MOSFET currently employed at the smallest scales that I know of; This is what started calling the feature size of the process node smaller and smaller past 24nm- at least for recent processes, the smallest parts of the "fin" were getting down in the 10-7nm range, and smaller.... but this isn't the size of the whole transistor, it needs multiple fins on either side to make the gate structure. So this was what happened when we end from talking about MOSFET feature size to the single-digit process node sizes that are essentially marketing terms now verses actual gate size.
There are actual density increases do to the packing of these type of FinFETs vs. more traditional MOSFETS. Thus the efficiency gains that have been happening. Among other reasons.
Not only is the density still improving, but new processes come with better characteristics for dealing with current leakage, smaller voltage requirements, and faster charge carrier propagation.
In other words, the transistors are being redesigned so that they work better.
Things are just not moving on the same rate they used to be, and costs are going up instead of down. But there is plenty of movement.
Moore’s law is over. There are a bunch of competing ways to measure advancements. What matters in the end is design and performance for a specific task.
If 3nm is merely a marketing term that has no relation to the distance between transistors than aren't we approaching a state where we could theoretically go into the negatives?
TL;DR: It's exponential, so it'll never go negative. After 3 comes 2. After 2 (at least for Intel) comes 1.8, or 18 Angstroms. See Wikipedia[0] for a reference.
Longer answer: (someone correct me where I'm wrong)
Historically, the number was a measure of the size of the transistor. 250 nm process nodes were producing planar transistors that were about 250 nm across. A node was then defined as the measure that brought a set increase in performance. In other words, going from 250 nm to 180 nm was the same improvement as going from 180 nm to 130 nm.
About the 45/32 nm mark, we reached the limits of making planar transistors. The machines couldn't get enough resolution to make them reliably. So, FinFET and others were invented as a way to increase performance to what was needed for the next generations. Essentially, the product has the performance of what planar transistors at said size would give, but they're not actually that size.
However, now that a few node generations have passed, even that's not true anymore. Now, it's just a marketing term, and you can't even compare performance between different manufacturers. TSMC's 5 nm has different performance than Samsung's and Intel's. All you can know is that TSMC's 3 nm will be better than their 5 nm.
The Intel 8088 chip was made on a 3 micrometer process node and a decade later they had to measure in nanometers for the 486 which launched on an 800 nm process node.
In terms of how much processing a single CPU core can accomplish (single thread performance) it plateaued about 15 years ago. So if your computation must be single threaded (audio effects processing, audio codecs, Photoshop, any app where computation has to finish before the next computation can begin, some real-time apps) then there has been little performance increase since then. However, if your computation can use multiple cores (video, graphics, user interfaces) the CPU power is approximately multiplied by the number of cores. More cores is like using more computers, so power use tends to increase, but since the task can be broken into multiple independent parts overall it gets done faster. Number of transistors is no longer a good measure of overall computional capability since often added transistors are not powered up most of the time (they are only used for special tasks like cryptography) but even so the number of transistors has also plateaued in the graph. Note the vertical scale is logarithmic, with each increment a factor of 10 over the line below it, so you need a LOT more transistors to keep that number-of-transistors curve going up the way it did in the past.
New technologies such as optical computation and quantum computing might help create even faster single threaded processors, but so far they have had no effect on consumer devices. A lot of the performance limits on CPU's are related to how fast you can feed them data (amount of RAM, RAM bandwidth, long term storage speed, bus bandwidths.) Such bus speeds have also been improving over time, but they still keep CPU's from running at top speed. We do not yet have widespread use of consumer systems where all the apps and data are stored in long term stable RAM rather than on an SSD (though some server apps do run from RAM only), so it is not just the CPU single threaded performance that matters. If apps and data start residing in RAM rather than on disk drives then CPU's can run faster but they'll use a lot more power as well, so cooling may become a bigger problem even if the bus systems can be made faster. Even if computation becomes really fast you generally need to then move the data to and from somewhere else for it to be useful (onto an SSD, a flash drive, network storage) so the speed of that transfer also limits how much computation can be done. So even if your processor could do a color transform on an entire video in a few microseconds, it may take an hour to transfer the video to your tablet, which means it takes an hour to free up space to do the next computation. Only applications which do a lot of math computation without much data I/O (like computing the Mandelbrot set) can really make full use of fast CPU's today, so increasing your I/O speed will usually have a bigger impact than increasing your CPU speed.
What is atomic scale to you? A Silicon atom is about 0.2nm across, and a team at Tsinghua University, China, have built a transistor gate with a length of 0.34 nm.[1] The difference between these lengths is 23 microns smaller than the diameter of the nucleus of a Silicon atom at 0.117nm.
> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. ... a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers... "3 nm" is used primarily as a marketing term by individual microchip manufacturers ... there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node
So can someone who is more familiar with it help me understand what progress we're making in terms of the physical aspect of the chips? Is transistor density still increasing? Are we using different materials? At a physical level what's different about this generation of chips?