Stop the misrepresentation and do your homework first please. MyHDL is as cycle accurate as Verilog & VHDL. It's based on the same event-driven paradigm - the paradigm that real industrial designers have been using to design real products for two decades. And you do not need conversion to Verilog/VHDL to achieve this - the core of MyHDL is a simulator.

The real difference is that in event-driven languages, clock events are explicit, instead of implicit like in Chisel and the whole array of dead HDLs that preceded it. So if history is any guide, Chisel is dead upon arrival.