Traditional "ISA wars" were about the cost of instruction decode & context-specific functionality. This really is over now: instruction decode costs hardly anything and context specific functionality is rarely used.
As far as I can tell, Mill have realised that the real fight is for cache; the most expensive thing you can do on a modern CPU is a data stall. So the intent is to change the execution model enough to change data access patterns and make prefetch work properly, along with more efficient use of the cache.
The next most expensive thing is a branch mispredict, and Mill attacks that strongly as well.
No Yes and Yes. Instruction decode wars aren't over, its just that the competition have plateaued :) One of the real big hurdles was decoding enough ops / cycle to compete, and the Mill's 33 ops/cycle is way way way more than everyone else, and due to the split stream and multi-phase decoding cunning.
And of course this is intimately dovetailed to cache, so Yes Yes Yes to everything you said too.
We aggressively speculate the cheap branches (which are the common type) and we aggressively inline, but mostly its to software pipeline loops (which make up 80% of most code).
As far as I can tell, Mill have realised that the real fight is for cache; the most expensive thing you can do on a modern CPU is a data stall. So the intent is to change the execution model enough to change data access patterns and make prefetch work properly, along with more efficient use of the cache.
The next most expensive thing is a branch mispredict, and Mill attacks that strongly as well.