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One of my "some day" / "thought experiment" projects is to create a small RISC-V RV32EC processor that would only be able to access 64k of its memory space, but would fit on a 40-pin IC: 16 pins of address, 8 pins of data, some interrupt and timing pins, etc. Basically like a 6502 or 8080/Z80 with the RV ISA. I can already think of some "fun" issues like requiring four read/write cycles per load/store operation.


I did a 16 bit processor that is compatible with RISC-V at the assembly language level but has its own binary encoding:

https://github.com/jeceljr/digitalCPUzoo/tree/main/drv16

It is meant as a helper processor in larger FPGA projects. These need less than 64KB of memory. drv16 is about the same size as the tiniest RISC-V (SERV, Glacial) without the huge performance penalties these have.




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