A few millions, not more -- maybe even less but I am not up to date with post Covid ASIC engineering costs.
We obviously want 100GbE because frankly why bother with less? So you need to translate https://github.com/corundum/corundum into an ASIC and then produce probably a few (ten) thousand ICs to make it worth it. However, you quite likely can get away with an old node -- the Intel XL710 40GbE chip, for example, is produced on a 28nm node.
So the production will be cheap, the initial ASIC engineering and prototyping is going to cost you a bit. But the (very) hard part is luckily already done.
You run into ToCToU issues. Even if a chip is "open", how can you be sure the chip you have corresponds to the specification? If that isn't a concern, any FPGA based SoC fits the bill, for example the MNT Reform Kintex-7 module (https://shop.mntre.com/products/mnt-rkx7-fpga-module).
You could use a Lattice ECP5 FPGA as a fully programmable/customizable NIC, you'll need an external PHY/transciever, this FPGA has 100% open source tooling available. There's an open source BMC implementation for this FPGA, it should be easy to modify to function as a plain Gigabit PCIe NIC.
