This is what the industry calls 2.5D technology. Intel has EMIB and TSMC has CoWoS. It’s one way the industry has been able to keep Moore’s Law limping along with chiplets.

It is like AMD Chiplets but all on one actual Die. The actual chips are produced as one chip. Chips with a bad 'half' get cut in half to become a M2 Max and a lower binned M2 Max. The Apple method here of using one die allows for much higher bandwidth than Chiplets.

The people who actually know what they're talking about disagree entirely: https://www.techinsights.com/blog/apple-joins-3d-fabric-port... https://www.techinsights.com/blog/apple-m1-ultra-advanced-pa...

AMD has been doing this with Zen/EPYC since 2017, and I'm not sure they were the first

I don't think any of those have used a silicon interposer. For examples of that, you have to look at the kind of devices using HBM RAM.

In the mid 90s IBM used it for multiple chips in POWER and S/390

So did Intel with the Pentium Pro and later Pentium 2, didn't they?

I believe Pentium 4D counts more than Pentium 2, but Pentium Pro does count and it was part of why it was so expensive (comparably). The slot-mounted CPU modules were essentially avoidances of multi-chip-modules or large easily broken (thus low yield) dies, and ran a normal PCB.

Apple started using this technique in 2022 for the M1 Ultra.