Hang on, is that actually true though? I was under the impression that shrinking process nodes represented a trade-off in terms of power consumption on the low end. There must be reasons why nobody makes a 14nm microcontroller, right?
Shrinking the process node means that you get less power consumption per transistor flip, but it can also increase the amount of static leakage current, which hurts designs that aim for energy budgets under say, 100uA.
I could be wrong, and I think that leakage can be mitigated by the lower operating voltages on smaller process nodes, but I don't believe it is as simple as "smaller process = more power efficient". If you're talking about GHz-scale application processors it holds true, but getting that sort of chip to idle at 0.05mA might be hard.
RAM can also consume a lot of power, if you have gigabytes of it. So until we have cheap high-density NVRAM, you might need a sort of 'hibernate' mode to get really low power consumption. And if you did that, you'd need to burn a bunch of energy to wake up and go back to sleep...busy, busy, busy.
I really am out of my depth to speak to specifics of 3nm or how the hell physics even works at that scale. I can just assert that mass adoption of ubiquitous and tactile computing has dependency on speed, locality, and energy consumption.
The chief reason no one makes a 14nm MCU is because the cost of designing on leading edge nodes is staggering and MCUs are a small market that doesn’t make that much money. Just as importantly, the MCU often tends to have a lot of analog and RF content on it, which actually gets easier worse as the nodes shrink
Shrinking the process node means that you get less power consumption per transistor flip, but it can also increase the amount of static leakage current, which hurts designs that aim for energy budgets under say, 100uA.
I could be wrong, and I think that leakage can be mitigated by the lower operating voltages on smaller process nodes, but I don't believe it is as simple as "smaller process = more power efficient". If you're talking about GHz-scale application processors it holds true, but getting that sort of chip to idle at 0.05mA might be hard.
RAM can also consume a lot of power, if you have gigabytes of it. So until we have cheap high-density NVRAM, you might need a sort of 'hibernate' mode to get really low power consumption. And if you did that, you'd need to burn a bunch of energy to wake up and go back to sleep...busy, busy, busy.