I really love Mill's design. Too bad it doesn't proceed fast enough due to lack of funding/backing. I guess I'm not the only one who couldn't afford to work without salary and pure stock compensation
related: are there any good sources on how you design for out of order processing? I have done a lot of "intro to electronic circuits" stuff that lead to a really basic register-based CPU, but when we get into stuff like OOO or branch prediction stuff I feel like I haven't really seen much on how it can work while keeping your sanity from a design perspective.
You keep a list (bitmap) of registers (hazards, really - MMU exceptions are hazards too) to be computed, you issue instructions whenever their hazards are cleared (will be cleared just before they read operands).
It is quite on par with the renaming machinery used in contemporary CPUs and is much, much easier to implement.
I worked on the TRIPS project in graduate school - specifically the compiler (my dissertation was about how to optimize the selection of dataflow subregions). I’d be curious what Doug and co. At Microsoft have done with E2 and whether they’ve actually cracked the compiler problem.
