There are three main conventional instruction set architectures: RISC, CISC, and VLIW.

ARM/Power/MIPS/RISC-V are all examples of a reduced instruction set architecture, RISC.

Of course, I completely misread that. I thought the OP was including the x86(which is obviously CISC) in that. Thanks.

Actually I was, CISC and RISC are both Von Neumann machines. ISA has more to do with encoding these days anyway.

Basically, despite how sophisticated the CPU of these machines becomes it is still trying to make the appearance of executing instructions in sequence.

Current x86 processors can execute many instructions in parallel under the correct conditions leading to Instructions Per Clock (IPC) greater much than one. However typical IPC hovers around 1 and some change, unless a lot of optimization effort is invested.

In order execution of an instruction sequence (or the appearance to the user of it) is the bottleneck that has led to single threaded CPU speed increases to all but disappear now that CPU frequency scaling has more or less halted.

x86 stopped being a pure CISC long time ago.

Sure, everything now reduces to microcode and micro-ops that are completely RISC but in a historical context about CPU architecture X86 is the poster child for CISC.

I think that's all the OP was getting at.

> but in a historical context about CPU architecture X86 is the poster child for CISC

Rather the DEC VAX and perhaps MC68k are poster childs of CISC. For a discussion of RISC vs. CISC see

> http://userpages.umbc.edu/~vijay/mashey.on.risc.html

or its extended version

> http://yarchive.net/comp/risc_definition.html

and look at the tables there. You will see that among the processors on the "CISC side", the Intel i486 is nearer to RISC than many other CISC architectures.