Generally true, though I think some of the proposed (future) SSE5 instructions may be three-operand -- or even four in the case of FMA ops (perhaps this is what you were subtly referring to by saying "yet").

Perhaps more importantly though, (again, AFAIK) x86 does not have any instructions that operate memory-to-memory in the way the article indicates. There are plenty of memory-to-register and register-to-memory (and register-to-register) ops, but the ALU ops generally don't combine a load and a store into a single instruction (some instructions like cmpxchg do for the purpose of providing atomicity, but those are a special case).