Anyone else puzzled by the post’s unclear references to briefings/questions that both went really well while also at the same time went downhill and dodged questions?
> After the rather solid pre-briefing, the basic questions SemiAccurate asked were either dodged or ignored, and things went downhill from there, it was another string of own-goals for no potential up side.
> We honestly tried to find a silver lining and were still trying even after the Anandtech numbers came out. (Note: And an update) The briefing went really well, it was unusually direct, questions were answered clearly where possible, and the marketing fluff was minimal. Disclosure was, as is the norm with Intel of late, best in class, and it all looked good for the writeup.
This article makes decent claims about power issues based on the architecture backport, but it lost me right here:
> Because Intel makes tens of millions of 14nm dies that are about 2x as large as Rocket Lake every year. They are called Xeons, specifically the HCC Xeon die which was 601.92mm^2 for Skylake-SP, larger for Cascade Lake. Intel unquestionably can make 14nm dies that are a multiple larger than Rocket, 10C would not be an issue at all if they wanted to manufacture it.
Have you seen the obscene physical size of those sockets? When you get larger than HEDT (LGA 2066 sockets) (and even then) the mere act of a user installing their own cpu becomes a dangerous enough proposition that Intel won’t even allow you to seat the cpu on the pin array. You have to slide Xeons into the heatsink clamp. They are limited to what a regular consumer expects to do.
Yes Intel screwed up royal on lithography processes, and probably need a cash infusion which they will likely get due to a newly competent CEO selling this stopgap to OEMs.
Is there a write-up anywhere that explains the likelihood of Intel actually figuring out how to keep moving down the process nodes again? At this rate AMD with TSMC will be 3-4 nodes ahead of Intel in a couple of years. If you believe the claim that intels 10nm node is equivalent to TSMCs 7nm node, well TSMC is already doing 3 and 4nm chips, and in high volume production on 5nm. Would love to hear that there is a plan not to make more stuff like RocketLake.
> After the rather solid pre-briefing, the basic questions SemiAccurate asked were either dodged or ignored, and things went downhill from there, it was another string of own-goals for no potential up side.
> We honestly tried to find a silver lining and were still trying even after the Anandtech numbers came out. (Note: And an update) The briefing went really well, it was unusually direct, questions were answered clearly where possible, and the marketing fluff was minimal. Disclosure was, as is the norm with Intel of late, best in class, and it all looked good for the writeup.